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(R)
CA3193, CA3193A
January 1998
Features
* Low VIO - CA3193A . . . . . . . . . . . . . . . . . . . . . . . . . .200V (Max) - CA3193 . . . . . . . . . . . . . . . . . . . . . . . . . . .500V (Max)
T T DUC D UC 1.2MHz, BiCMOS Precision PRO UTE PRO er at TE OLE UBSTIT rt Cent tsc Operational Amplifiers / O B S LE S u ppo c om SSIB hnical S .intersil. w A PO ec FOR act our T IL or ww Description nt RS E co -INT -888 1 The CA3193A and CA3193 are ultra-stable, precision
instrumentation, operational amplifiers that employ both PMOS and bipolar transistors on a single monolithic chip. The CA3193A and CA3193 amplifiers are internally phase compensated and provide a gain bandwidth product of 1.2MHz. They are pin compatible with the industry 741 series and many other IC op amps, and may be used as replacements for 741 series types in most applications. The CA3193A and CA3193 can also be used as functional replacements for op amp types 725, 108A, OP-5, OP-7, LM11 and LM714 in many applications where nulling is not employed. Because of their low offset voltage and low offset voltage vs temperature coefficient the CA3193A and CA3193 amplifiers have a wider range of applications than most op amps and are particularly well suited for use as thermocouple amplifiers, high gain filters, buffer, strain gauge bridge amplifiers and precision voltage references. The two types in the CA3193 series are functionally identical. The CA3193A and CA3193 operate from supply voltages of 3.5V to 18V.
* Low VIO/T - CA3193A . . . . . . . . . . . . . . . . . . . . . . . . . 3V/oC (Max) - CA3193 . . . . . . . . . . . . . . . . . . . . . . . . . . 5V/oC (Max) * Low IIO and II * Low IIO/T: CA3193. . . . . . . . . . . . . . .150pA/oC (Max) * Low II/T: CA3193 . . . . . . . . . . . . . . . . 3.7nA/oC (Max)
Applications
* Thermocouple Preamplifiers * Strain Gauge Bridge Amplifiers * Summing Amplifiers * Differential Amplifiers * Bilateral Current Sources * Log Amplifiers * Differential Voltmeters
Part Number Information
PART NUMBER TEMP. RANGE (oC) -25 to 85 0 to 70 PACKAGE 8 Ld PDIP 8 Ld PDIP PKG. NO. E8.3 E8.3
* Precision Voltage References * Active Filters * Buffers * Integrators * Sample-and-Hold Circuits * Low Frequency Filters
CA3193AE CA3193E
Pinout
CA3193 (PDIP) TOP VIEW
OFFSET NULL INV. INPUT NON-INV. INPUT V-
1 2 3 4
8
NC V+ OUTPUT OFFSET NULL
+
7 6 5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 60 All other trademarks mentioned are the property of their respective owners.
FN1249.4
CA3193, CA3193A
Absolute Maximum Ratings
DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V+ -4), VInput Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 2) . . . . . . . . . . . . . . . . Indefinite
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range CA3193A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC CA3193 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. Short circuit may be applied to ground or to either supply.
Electrical Specifications
PARAMETER Input Offset Voltage VIO Input Offset Voltage Temperature Coefficient (Over Specified Temperature Range for Each Device) Input Offset Current Input Offset Current Temperature Coefficient (Over Specified Temperature Range for Each Device) Input Bias Current Input Bias Current Temperature Coefficient Input Noise Voltage Input Noise Voltage Density
TA = 25oC, VSUPPLY = 15V, Unless Otherwise Specified TEST CONDITIONS 25oC TMAX VIO/T CA3193 SYMBOL VIO MIN TYP 300 1 MAX 500 725 5 MIN CA3193A TYP 140 1 MAX 200 380 3 UNITS V V V/oC
25oC TMAX
IIO IIO/T
-
5 0.04
10 17 0.15
-
3 0.03
5 11 0.10
nA nA nA/oC
25oC TMAX
II II/T
-
20 0.15 0.36 25 25 24 24 22 12 0.83 0.80 0.75 0.72 0.60 -13.5 to 11.5 110 3.16 130 0.316 13.5 110 115
40 207 3.70 20 10 10 10 -
-12 110 100 13.0 110 -
10 0.10 0.36 25 25 24 24 22 12 0.83 0.80 0.75 0.72 0.60 -13.5 to 11.5 115 1.78 130 0.316 13.5 115 125
20 83 1.18 20 10 3.16 10 -
nA nA nA/oC VP-P nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz pAP-P pA/Hz pA/Hz pA/Hz pA/Hz pA/Hz V dB V/V dB V/V V dB dB
0.1 to 10Hz f = 10Hz f = 100Hz f = 1000Hz f = 10kHz f = 100kHz
eN P-P eN
Input Noise Current Input Noise Current Density
0.1 to 10 Hz f = 10Hz f = 100Hz f = 1000Hz f = 10kHz f = 100kHz
IN P-P IN
-
Common-Mode Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio VIO/V Maximum Output Voltage Swing RL 2k Large-Signal Voltage Gain (VO = 10) RL 2k RL 10k VCM = VICR
VICR CMRR PSRR VOM AOL
-12 100 100 13.0 100 -
61
CA3193, CA3193A
Electrical Specifications
PARAMETER Short-Circuit Output Current to the Opposite Rail Slew Rate Gain-Bandwidth Product RL 2k, AV = +1 AOL = 0dB, RL = 2k, CL = 100pF, VIN = 20mVP-P , f = 1kHz RL = , VS = 15V VIN = 20mVP-P, f = 1kHz TA = 25oC, VSUPPLY = 15V, Unless Otherwise Specified (Continued) TEST CONDITIONS CA3193 SYMBOL IOM+, IOMSR fT MIN -25 TYP 7 0.25 1.20 MAX 25 MIN -25 CA3193A TYP 7 0.25 1.20 MAX 25 UNITS mA V/s MHz
Rise and Fall Time Supply Current
tR I+
-
0.29 2.3
3.5
-
0.29 2.3
3.5
s mA
Test Circuits and Waveforms
10K V+ 2 +15V 6 VOUT 4 V-15V V OUT V IO = -------------100
+
7
100
3
FIGURE 1. INPUT OFFSET VOLTAGE TEST CIRCUIT
10K
0
+15V 10K +10V 0V +10V 1kHz VIN 3 5K + 4 -15V VOUT = -VIN 2
-
7 6 RL 10K VOUT 200pF
0
Top Trace: Input Voltage, Bottom Trace: Output Voltage Vertical Scale: 10V/Div., Horizontal Scale: 0.1ms/Div. FIGURE 2B. RESPONSE TO 1kHz, 20VP-P SQUARE WAVE FIGURE 2. INVERTING AMPLIFIER
FIGURE 2A. TEST CIRCUIT
10K +10V 0V +10V VIN
+15V 3 + 7 6 VOUT 4 -15V SIMULATED LOAD 200pF 2K
0
2
-
0
Top Trace: Input Voltage; Bottom Trace: Output Voltage Vertical Scale: 10V/Div.; Horizontal Scale: 0.1ms/Div. FIGURE 3A. TEST CIRCUIT FIGURE 3B. RESPONSE TO 20VP-P, 1kHz SQUARE WAVE INPUT
62
CA3193, CA3193A Test Circuits and Waveforms
(Continued) FIGURE 3. VOLTAGE FOLLOWER
LOW PASS FILTER DC TO 10Hz A 3.3k 1% CA3193 3 100 1% 100 1% 20k 4 5 1 20k 6 4.7F 1% 1M 2.2F 1% HIGH PASS FILTER 0.1 TO 10Hz B SCOPE INPUT RESISTANCE
2.2M 1%
+15V 7 2
1k -15V
V OUT P-P V NOISE = --------------------------3 22x10
FIGURE 4A. TEST CIRCUIT - 0.1Hz TO 10Hz
FIGURE 4B. OUTPUT A WAVEFORM - 0Hz TO 10Hz NOISE
FIGURE 4C. OUTPUT B WAVEFORM - 0.1Hz TO 10Hz NOISE
FIGURE 4. LOW FREQUENCY NOISE
Functional Block Diagram
2.3mA BIAS NETWORK 3A + 3 INPUT A 2000 A7 950A 70A 660A 20pF 25K A 75 7.5K A1 6 OUTPUT 6pF 600A 7 V+
2
1
5 4 V-
OFFSET NULL
63
CA3193, CA3193A Schematic Diagrams
7 V+
Q7
Q8
Q14
Q12 25K 20pF 7.5K D7 100
60 6 OUTPUT
6pF
D8 Q13 Q17 Q15 Q19 Q18
60
2 INPUT
1K
Q1
Q2 Q30
Q16
D1 1K D2
D9 D13
680
6K 4 V-
3 +
FIGURE 5. CA3193 SIMPLIFIED SCHEMATIC DIAGRAM
7 R1 3K R2 3K R3 3K D3 D4 D5 Q9 Q10 D6 Q3 Q4 Q7 Q8 R5 1.6K 20pF Q14 Q12 R6 D7 7.5K Q13 D8 Q15 R16 6K R17 25K R14 3.7K Q30 D9 Q24 Q26 Q27 D10 Q25 Q28 Q29 D11 D12 Q31 R13 15K D14 4 5 OFFSET NULL 1 VQ18 D13 R15 680 Q17 Q19 Q16 R9 60 R8 100 R10 60 OUTPUT 6 Q11 R4 120 V+
Q5
Q6
2
R11 1K
Q1
Q2 Q20 Q21
6pF R7 100K Q22 Q 23
D1 INPUTS R12 3 + 1K D2
FIGURE 6. SCHEMATIC DIAGRAM OF CA3193A AND CA3193
64
CA3193, CA3193A Application Information
Circuit Description The block diagram of the CA3193 amplifier shows the voltage gain and supply current for each of its four amplifier stages. Simplified and complete schematic diagrams of the CA3193 amplifier are shown in Figures 5 and 6, respectively. A quad of physically cross-connected NPN transistors comprise the input-stage differential pair (Q1, Q2 in Figures 5 and 6); this arrangement contributes to the low input offsetvoltage characteristics of the amplifier. The ultra-high gain provided in the first stage ensures that subsequent stages cannot significantly influence the overall offset-voltage characteristics of the amplifier. High load impedances for the input-stage differential pair (Q1, Q2) are provided by the cascode-connected PNP transistors Q3, Q5 and Q4, Q6, thereby contributing to the high gain developed in the stage. The second stage of the amplifier consists of a differential amplifier employing PMOS/FETs (Q7, Q8 in Figures 5 and 6) with appropriate drain loading. Since Q7 and Q8 are M0S/FETs, their loading on the first stage is quite low, thereby making an additional contribution to the high gain developed in the first stage. The second stage is also configured to convert its differential signal to a single-ended output signal by means of current mirror D9, Q30 (Figures 5 and 6) to drive subsequent gain stage. The third stage of the amplifier consists of Darlingtonconnected NPN transistors (Q17, Q19 in Figures 5 and 6), driving the quasi-complementary Class AB output stage (Q14 and Q15, Q16 in Figures 5 and 6). Output-stage shortcircuit protection is activated by voltage drops developed across the 60 resistors adjacent to the output terminal (R9 and R10, Figure 6). When the voltage drop developed across either of these resistors reaches a potential equal to 1 VBE, the respective protective transistor (Q12 or Q13) is activated and shunts the base drive from the bases of the output stage transistors (Q14 and Q15, Q16). Internal frequency compensation for the CA3193 amplifier is provided by two internal networks, a 6pF capacitor connected between the input-stage transistor collectors and the node between the third and output stages and a second network, consisting of a 20pF capacitor in series with a 7.5k resistor connected between the input and output nodes of the third stage. Offset Voltage Nulling The input offset voltage can be nulled to zero by any of the three methods shown in the table below. A 10K potentiometer between terminals 1 and 5, with its wiper returned to V-, will provide a gross nulling for all types. For finer nulling, either of the other two circuits shown below may be used, thus providing simpler improved resolution for all types.
CAUTION: The CA3193 amplifiers will be damaged if they are plugged into op amp circuits employing nulling with respect to the V+ supply bus.
Offset Voltage Nulling
VR 1 VR 5 10K 1K 5 R 1 V5 R
OFFSET NULLING CIRCUITS TYPE CA3193A CA3193
1
RESISTOR R VALUE 10K 10K Gross Offset Adjustment
RESISTOR R VALUE 50K 20K
RESISTOR R VALUE 10K 5K
Finer Offset Adjustments
65
CA3193, CA3193A Typical Applications
+15V V+ a Va 3 2 + 7 6 4 -15V R1 1K R2 9K +15V 2 R3 1K V2 R1 10K R3 10K 2 20K +15V V1 R2
CA3193
R
R
-
+
7 6
VOUT RL
R
R + R
CA3193 3 R4 20K 4
-15V
+
7 6
R4 9K VOUT
ALL RESISTANCE VALUES ARE IN OHMS.
CA3193 3 b Vb 4 -15V
R 4 R 1 + R 2 R 2 V OUT = V 2 -------------------- -------------------- - V 1 ------ R 3 + R 4 R 1 R 1 R2 R4 If R 4 = R 2 , R 3 = R 1 and ------ = -----R1 R3 R 2 THEN V OUT = ( V 2 - V 1 ) ------ R 1 For values above VOUT = 2(V2 - V1): If AV is To be made 1 and if R1 = R3 = R4 = R with R2 = 0.999R (0.1% mismatch in R2) Then VOCM = 0.0005 VIN or CMRR = 66dB Thus, the CMRR of this circuit is limited by the matching or mismatching of this network rather than the amplifier. FIGURE 8. DIFFERENTIAL AMPLIFIER (SIMPLE SUBTRACTER) USING CA3193
R2 R4 R4 V OUT = - V a ------ + 1 ------ + V b ------ + 1 R1 R3 R3 R3 R1 For Ideal Resistors with ------ = -----R2 R4 R4 V OUT = V b - V a ------ + 1 R3 V OUT R4 A = ------------------- = ------ + 1 Vb - Va R3
FOR VALUES ABOVE VOUT = (Vb - Va) (IO)
FIGURE 7. TYPICAL TWO OP AMP BRIDGE-TYPE DIFFERENTIAL AMPLIFIER
R2 1M
V3 2
R3 10K RF 20K
+
7
+15V 6 R5 1K V1 RL (0 TO 3.0k) WITH V = 1V V2 IL
R2 10K
3 R1 2M R3 2M
CA3193 4
-15V R4 1M
+15V R1 10K 3 R4 2.8K 2
+
7 6
CA3193 4
RS V
RL -15V
ALL RESISTORS ARE 1% IF R1 = R3 AND R2 R4 + R5, THEN IL IS INDEPENDENT OF VARIATIONS IN RL FOR RL VALUES OF 0 TO 3k WITH V = 1V
RF RF RF V OUT = - ------- V 1 + ------- V 2 + ------ 3 -V R1 R2 R3
VOUT = - (2V1+ 2V2 + 2V3) ALL RESISTANCE VALUES ARE IN OHMS.
VR 4 V V ( 1M ) I L = -------------- = ------------------------- = ------- = 500A 2K ( 2M ) ( 1K ) R 3 R5 FIGURE 9. USING CA3193 AS A BILATERAL CURRENT SOURCE
FIGURE 10. TYPICAL SUMMING AMPLIFIER APPLICATION
66
CA3193, CA3193A Typical Applications
(Continued)
V+ +15V 22M 22M 22M 7 + 10K 2 CA3193 6 5 4 1 THERMOCOUPLE 0.1F 20K -15V 20K 499K 1K 10K 1K 2K 8.2K VOUT
3
-
0-1mA
ALL RESISTORS ARE 1%. ALL RESISTORS ARE IN OHMS.
FIGURE 11. THE CA3193 USED IN A THERMOCOUPLE CIRCUIT
The CA3193 is an excellent choice for use with thermocouples. In Figure 11, the CA3193 amplifies the
generated signal 500 times. The three 22M resistors will provide full-scale output if the thermocouple opens.
Typical Performance Curves
300 400 CA3193 (0oC to 70oC) INPUT OFFSET VOLTAGE ( V) 300 INPUT OFFSET VOLTAGE (V) CA3193
200
CA3193A (-25oC to 85oC) 200
100
CA3193A
100 0 0 0 -50 500 1000 1500 TIME AT AMBIENT TEMPERATURE = 125oC (HOURS) 0 50 100 150 0 385 770 1155
TEMPERATURE (oC)
EQUIVALENT TIME AT TEMPERATURE = 25oC (DAYS)
FIGURE 12. TYPICAL INPUT OFFSET VOLTAGE TEMPERATURE CHARACTERISTIC
FIGURE 13. INPUT OFFSET VOLTAGE vs TIME
67
CA3193, CA3193A Typical Performance Curves
40 INPUT OFFSET CURRENT (nA)
(Continued)
8
INPUT BIAS CURRENT (nA)
30
6
20
CA3193 (0oC to 70oC)
4 CA3193
10
CA3193A (-25oC to 85oC)
2 CA3193A
0 -50
0 0 50 100 150 -50 0 50 100 150 TEMPERATURE (oC) TEMPERATURE (oC)
FIGURE 14. TYPICAL INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 15. TYPICAL INPUT OFFSET CURRENT vs TEMPERATURE
EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz)
TA = 25oC
EQUIVALENT INPUT NOISE CURRENT (pA/Hz)
103
102
5 POWER SUPPLY CURRENT (mA)
TA = -55oC TO 125oC
4
102
10
eN 101
3
iN
1
2
1 101
0.1 102 103 FREQUENCY (Hz) 104 105
1 2 6 10 14 18 22 POWER SUPPLY VOLTAGE (V)
FIGURE 16. INPUT NOISE VOLTAGE AND CURRENT DENSITY vs FREQUENCY
160 -100
FIGURE 17. POWER SUPPLY CURRENT vs SUPPLY VOLTAGE
150
TA = 25oC
TA = 25oC
120 OPEN LOOP GAIN (dB)
-50 PHASE ANGLE (DEGREE) AOL 0 OPEN LOOP GAIN (dB) 140
80
40
50
130
0
OL
100
120
-40
150
-80 0.1 101 103 105 FREQUENCY (Hz)
200 107
110 2 6 10 14 18 POWER SUPPLY VOLTAGE (V) 22
FIGURE 18. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE
FIGURE 19. OPEN LOOP GAIN vs POWER SUPPLY VOLTAGE
68
CA3193, CA3193A Typical Performance Curves
140 4 INPUT AND OUTPUT EXCURSIONS FROM TERMINAL 4 (V) 3 2 1 0 -1 -2 -50 0 50 100 150 0 4 8 TEMPERATURE (oC) 12 16 20 SUPPLY VOLTAGE (V) 24 28 VOUT VICR
(Continued)
TA = 25oC, UPPER SUPPLY VOLTAGE FOR CA3193A AND CA3193 IS 18V
OPEN LOOP GAIN (dB)
130
120 CA3193A (-25oC to 85oC)
110 CA3193 (0oC to 70oC)
100
FIGURE 20. OPEN LOOP GAIN vs TEMPERATURE
FIGURE 21.
MAXIMUM OUTPUT VOLTAGE SWING (VP-P)
40 35 30 25 20 15 10 5 0 1
INPUT AND OUTPUT EXCURSIONS FROM TERMINAL 7 (V)
TA = 25oC
RL = 2K V+ = 15V V- = -15V
1
0
-1
VOUT
-2
-3
VICR
-4
101
102
103
104
105
-5 0 4 8 12 16 20 24 28 SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
FIGURE 22. MAXIMUM UNDISTORTED OUTPUT VOLTAGE vs FREQUENCY
FIGURE 23. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE vs SUPPLY VOLTAGE
69
CA3193, CA3193A Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 8
2.93
70

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